An important goal in the development of new generations of DMOS power transistors is to reduce the on resistivity Ron*A. As a result of this it is possible on the one hand to minimize the static power loss; on the other hand it is possible to achieve higher current densities, whereby smaller and less expensive chips can be used for the same total current. However, a very good avalanche strength is furthermore also required for the off-state case. Measures for reducing the on resistivity often bring about an impairment of the avalanche behavior, however.